Here’s a classic example of a self-biased voltage reference, shown in Figure 1. You’ll see this circuit in almost every analog IC design textbook. But here’s the tricky part: deciding which transistors should be diode-connected.

Most books just throw equations at you and briefly mention start-up circuitry, without really explaining the intuition behind it. In simulations, it feels straightforward—you connect the diodes one way, the circuit crashes into the rails and fails. Flip the connections, and suddenly it works.

But starting design this way isn’t ideal. Why? Because we’re relying entirely on trial-and-error and simulation accuracy, without actually understanding the principle behind the circuit. That’s where the real question comes in: what’s really happening inside this circuit?

The name of this circuit says it all. The transistor network formed by M1–M4 biases itself, creating a loop (shown with the red arrow). What’s unusual here is that this loop works through positive feedback.

Imagine for a moment that we remove the PNPs and resistor, and connect points A and B directly to ground. Now, if the drain voltage of M1 increases by ΔV, the drain current of M3 also rises. That, in turn, boosts the current of M4. A stronger M4 current increases its VSG, which pushes M1’s current even higher. The result? The drain current grows, ΔV gets larger, and the positive feedback keeps reinforcing itself. Without intervention, any small noise gets amplified until the node voltages slam into the rails.

To avoid this runaway situation, we need another feedback loop—the one marked with the green arrow. This time it’s negative feedback. The resistor RE adds source degeneration to M4, reducing its gain. Remember, M4 isn’t diode-connected; it’s acting as a common-source amplifier.

Now, let’s flip the scenario. What if we swap the diode connections, tying them to M1 and M4 instead of M2 and M3? The answer is straightforward: all node voltages shoot to the rails. Why? Because the degeneration resistor is now tied to a diode-connected transistor instead of the amplifier. That means the negative feedback is gone, and the positive feedback dominates unchecked.

Now that we’ve set n and RE, the voltages at nodes A and B should match, thanks to the M3–M4 current mirror (and M1–M2 reinforcing it). The voltage difference between the VEB of Q1 and Q2 generates a PTAT current across RE, and through M1–M2 as well.

But there’s still a catch. If you ramp up the supply voltage with a certain rise time, the circuit might not start properly. Why? Because the diodes can “copy” zero current, producing no bias at all—even if your DC simulations show a steady current. To fix this, we need a start-up circuit that injects a finite current for a short time. Once that current is provided, the “zero-current” state is eliminated, and the circuit settles into the intended bias condition.

Another limitation of the Figure 1 circuit is its poor supply immunity, despite being simple to design. Ideally, reference circuits should be process-, voltage-, and temperature-independent (or at least predictable, like in the PTAT case). The voltage part is especially tricky and involves two aspects:

1. Power supply regulation – the supply may carry noise or frequency-dependent components.

2. Supply variation – the voltage itself may shift or need to operate within a range for different designs.

In both cases, we want supply-independent biasing. Back to Figure 1: if the supply voltage changes by ΔV, the drain currents of M1–M2 increase. RE provides some negative feedback to counter this, but it’s weak protection. Why? Because the circuit only uses a common-source amplifier with a degeneration resistor. If the supply shifts widely (say from 3.3 V to 5.5 V), the drain currents will still drift. The root problem is the insufficient gain of the feedback loop.

So, how do we fix the weak supply immunity problem? The answer is to increase the loop gain. In Figure 2, the NMOS transistors M3–M4 from Figure 1 are removed, and instead we add an operational amplifier. A simple differential pair can serve as the op-amp. The op-amp output drives M1 and M2, while their drains feed directly back into the op-amp inputs. In closed loop, the op-amp forces its inputs to the same voltage (assuming high enough gain), so nodes A and B can be treated as equal.

The idea here is to generate a current through RE that depends on the thermal voltage difference, VT—giving us a PTAT current. But there’s a subtle question: what happens if we connect the op-amp inputs the opposite way? To answer that, we need to build intuition about the feedback loops.

Looking at the schematic, you’ll notice the red and green arrows. M1 and M2 act as common-source PMOS amplifiers, with equal VSG voltages, so they drain the same current. For node A (negative input), if the voltage increases by ΔV, M1’s drain current rises further because both the op-amp and M1 have negative gain. That creates a positive feedback loop (red arrow). For node B, if the voltage increases by ΔV, M2 works to lower its drain voltage, forming a negative feedback loop (green arrow).

The key insight is that the negative feedback loop must overpower the positive one to keep the nodes from running to the rails. The loop gains depend on op-amp gain, M1–M2 transconductance, their output resistances, and the impedance seen from A and B to ground. The first three terms are identical for both loops, since the op-amp forces M1 and M2 to drain the same current. The only difference lies in the fourth term.

So, if we want stronger negative feedback, we need to connect the resistor to the positive input side of the op-amp. That way, the negative loop gain dominates, stabilizing the circuit.

The last piece to consider is the compensation capacitor you see connected from the transistor gates to the supply. Earlier, we used a basic differential pair as the op-amp, which has one high-impedance node and a single pole. But once M1–M2 are added, the circuit effectively becomes a two-stage amplifier.

At very low frequencies, the negative feedback side has more gain, which is good. But as frequency increases, the phase shift grows, and at some point the feedback polarity can flip. That’s risky. To prevent this, we add a compensation capacitor between the gates of M1–M2 and VDD (or ground). This improves the phase margin of the loop and makes the circuit unconditionally stable.

Distinguishing the feedback signs is actually simple, as described earlier. Before jumping straight into simulations, all you really need is some basic intuition about how the circuit works. The rest is simulator work. For self-biased references, two key questions must be answered during design:

1. Does the circuit start up and settle into the intended bias point? (transient simulation)

2. Does the negative feedback loop have enough phase margin to guarantee unconditional stability? (AC or STB simulation)

Answer those two questions, and you’re set!

Mete                                                                                                                                06/21/2025