Here, we have a classic example about self-biased voltage reference in Figure 1. This circuit can be found in almost every analog IC design textbook. Nevertheless, it is hard to think about which transistors should be diode connected. Why? Because most of books just give equations and mention start-up circuitry. In simulation part, it is easier than that. If you connect diodes as opposite, the circuit hits the rails and doesn't work correctly. Then, you change connections, and it works well.

However, this is an improper way to begin design. First of all, we don't have any intuition about working principle. Moreover, our design relies on accuracy of our simulation results. After those, a real question should be risen? What's happening in that circuit?

Name of the circuit manifests itself. M1-2-3-4 transistors network biases themselves forming a loop circulating red arrow. Unusually, this is a positive feedback mechanism. Suppose that we don't have PNP's & resistor, and A & B directly connected to ground. If we increase drain voltage of M1 about ΔV, drain current of M3 increases, and it leads to increase current of M4 too. Increased M4 current give rises to larger VSG, and it increases M1 current too. Larger drain current increases ΔV much more. As a result, a positive feedback mechanism works. If you don't change the voltage of any node, the circuit biases itself by using diodes in two branches. In reality, any noise can be amplified, and node voltages hit the rails. 

To prevent this risky situation, we need another feedback which is encircled green arrow (For clarity, you can ignore PNP transistors). Contrary to previous one, this is negative feedback. RE degenerates' source of M4 and reduces the gain of transistor. Remember! M4 is not a diode connected transistor. It is a common-source amplifier. Now, let's consider the opposite case: If we change diode connections to M1 & M4 from M2-3, what will happen in the circuit? The answer is clear: All node voltages go rails because there is no negative feedback anymore to beat the positive one. Because, we connected degeneration resistor to the diode connected transistor, not to amplifier one. 

Now, we determined n and RE. As a result, voltage in A & B should be equal to each other due to M3-4 current mirror (M1-2 also forces it). Voltage difference between VEB of Q1-2, creates PTAT current on RE, and M1-2 too.

There is still an unwanted case of the circuit. If you ramp up the supply voltage with a certain rising time, you cannot guarantee that the circuit starts up. Diodes can copy "zero" current and produce no current even if your DC simulation results show a certain DC current. To overcome this problem, a start-up circuitry should be added to give a finite current in a certain time. After giving that current, you eliminate "zero current" case, and the circuit works in bias conditions that you intend.

The circuit given in Figure 1 has poor supply immunity even if it is simple to design. The reference circuits generally are intended to be process, voltage & temperature independent (or predictable as in PTAT case). Voltage part is tricky and refers 2 things. First one is power supply regulation. Power supply in the design might include noise or frequency dependent component. Second, supply voltage might be shifted, or it should be in an interval to be used in different designs. In both cases, we need supply independent biasing circuits. Let's back to Figure 1. If you change supply voltage about ΔV, what will happen in the circuit? Actually, it is straightforward: Drain currents of M1-2 increases, however RE prevents it by negative feedback. This is poor protection to supply voltage change because we are only using a common-source amplifier with a degeneration resistor. At the end, drain currents will shift if change supply voltage in wide range (For example, In Vdd=3.3V case, you change it 3.3V to 5.5V). The main problem is insufficient gain of the feedback loop.

To overcome this, we need to increase loop gain. In Figure 2, M3-4 NMOS transistors in Figure 1 are omitted, and an operational amplifier is added. A basic differential pair might be used to implement the operational amplifier. M1 and M2 are driven by opamp output, and their drains are directly connected to opamp input. In a closed loop, opamp tries to keep its inputs at the same voltage if its gain is high enough. Hence, we can assume that A and B nodes have equal voltage. The approach is to use to produce current on RE which depends on thermal voltage difference, VT (It corresponds proportional to absolute temperature, PTAT). However, another question arises when we ask before: What happens if we connect the opamp input opposite sides? To answer the question, we need intuition about the circuit.

There are red and green circled arrows in the schematic. M1 and M2 works as common source PMOS amplifier, and their VSG voltages are the same. Hence, they drain the same current. For negative input A, if the voltage increases ΔV, M1 drain increases more due to negative gain of both opamp and M1. As a result, red circle is positive feedback loop. For node B, if the voltage increases ΔV, M2 tries to decrease its drain voltage. Hence, there is negative feedback. Now, consider the gain of these two loops when we did it above. According to our inspection, negative feedback loop has to beat the positive one to prevent nodes to go rails. It means, we need more gain in negative feedback side. For clarity, output resistance of Q1 and Q2 might be assumed as 1/gm and the same (It is correct because transconductance of bipolar transistors is equal to Ic/VT). The loop gains depend on opamp gain, M1-2 transconductances, M1-2 output resistances & impedances when you look from A & B to the ground. First 3 terms are the same for both loop because opamp forces to them to drain the same current. The fourth one is the only difference between two loops. If we want to have more gain in negative side, we need to connect resistance to positive input side of opamp (because we have M1-2 common source amplifier too!).

The last point is the capacitance that you see connected to transistor gates to supply. As it is mentioned above, we used basic differential pair as opamp. We know that it has 1 high impedance node and 1 pole. However, when we add M1-M2, it forms 2-stage amplifier. Our circuit has more gain in negative sides at very low frequencies. However, when the frequency increases, phase shift increases, and feedback polarity will change at some certain frequency. To prevent this, we need to add a compensation capacitor between gates of M1-2 & VDD or ground. It will improve phase margin of the loop and make the circuit unconditionally stable.

To distinguish signs and feedback is simple as I described above. Before blindly starting the design, there is only need to basic intuition about the circuits. Rest of them is related to simulator. For self-biased references two question should be answered during design. First, is the circuit start up and settle as you intended (transient simulation)? Second, is the negative feedback loop have phase margin to make the circuit unconditionally stable (ac or stb simulation)? That's all you need!

Mete                                                                                                                                                  06/21/2025